Dual RF LDMOS Bias Controllers
with I 2 C/SPI Interface
I 2 C HIGH-SPEED-MODE TIMING CHARACTERISTICS (Note 12, see Figure 2)
(GATEV DD = +5.5V for MAX1385, GATEV DD = +11V for MAX1386, AV DD = +5V, DV DD = 2.7V to 5.25V, external V REFADC = +2.5V,
external V REFDAC = +2.5V, C REF = 0.1μF, T A = -40°C to +85°C, unless otherwise noted).
PARAMETER
Serial-Clock Frequency
SYMBOL
f SCL
CONDITIONS
MIN
0
TYP
MAX
3.4
UNITS
MHz
Setup Time Repeated START
Condition
Hold Time Repeated START
Condition
SCL Pulse-Width Low
SCL Pulse-Width High
Data Setup Time
t SU;STA
t HD;STA
t LOW
t HIGH
t SU;DAT
160
160
160
60
10
ns
ns
ns
ns
ns
Data Hold Time
Rise Time of SCL Signal,
Receiving
t HD;DAT
t RCL
(Note 17)
0
10
70
40
ns
ns
Rise Time of SCL Signal After a
Repeated START Condition and
After an Acknowledge Bit,
t RCL1
10
80
ns
Receiving
Fall Time of SCL Signal,
Receiving
Rise Time of SDA Signal,
Receiving
Fall Time of SDA Signal,
Transmitting
Setup Time for STOP Condition
Capacitive Load for Each Bus
Line
Pulse Width of Spikes That are
Suppressed by the Input Filter
t FCL
t RDA
t FDA
t SU;STO
C b
t SP
(Note 18)
10
10
10
160
0
40
80
80
100
10
ns
ns
ns
ns
pF
ns
8
_______________________________________________________________________________________
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